The eDP v1.4a standard leverages the VESA DisplayPort (DP) Standard v1.3, published in September 2014, as a base specification. That standard’s new higher HBR3 link rate, which operates at 8.1 Gbps per lane, is now also part of eDP v1.4a. With both HBR3 and the DSC v1.1 standard included, the latest eDP standard can support embedded panels with up to 8K resolution. For embedded display applications, DSC is most often used to decrease video interface data rate or wire count, as well as reduce display frame buffer size, thereby reducing system power usage to extend battery life. It also enables reductions in system complexity and form factor.
An entirely new feature in eDP v1.4a is “Multi-SST Operation,” or MSO, which supports a new type of display architecture that VESA calls “Segmented Panel Display.” Segmented Panel Display is designed to enable thinner, lighter and lower-cost panels that use less power. In operation, MSO allows the four high-speed eDP data lanes within the eDP interface to be divided up between either two or four independent panel segments. For lower resolutions, two lanes can be used to support two panel segments. This panel segmentation enables a higher level of integration on high-resolution displays; each segment can contain a separate timing controller with integrated source drivers.
eDP 1.4a also includes refinements to the partial update capability for Panel Self Refresh (PSR) that was introduced in eDP 1.4. Partial update enables the system video processor, or GPU, to update only the portion of the display that has changed since the video frame update, further saving system power.
It is anticipated that eDP 1.4a will be used within systems by 2016.